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A Transformer-based Syntax Tree Decoder for Handwritten Mathematical Expression Recognition
ZHOU Bohan, CAO Jian, WANG Yuan
Acta Scientiarum Naturalium Universitatis Pekinensis    2023, 59 (6): 909-914.   DOI: 10.13209/j.0479-8023.2023.085
Abstract294)   HTML    PDF(pc) (551KB)(186)       Save
Most of the existing tree-structured decoding methods of handwritten mathematical expression recognition are based on the recurrent neural networks, which have low training efficiency and complicated training process. In order to prove this problem, the authors propose a handwritten mathematical expression recognition model based on Transformer structure, which can decode the syntax tree of expressions directly. Experimental results show that the proposed tree-structured decoding method achieves better performance than the string decoding methods base on Transformer on several datasets of handwritten formula recognition tasks, and show the potential to surpass recurrent neural network tree decoding methods.
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AdaPruner: Adaptive Channel Pruning and Effective Weights Inheritance
LIU Xiangcheng, CAO Jian, YAO Hongyi, XU Pengtao, ZHANG Yuan, WANG Yuan
Acta Scientiarum Naturalium Universitatis Pekinensis    2023, 59 (5): 764-772.   DOI: 10.13209/j.0479-8023.2022.115
Abstract287)   HTML    PDF(pc) (772KB)(207)       Save
Previous channel pruning methods require complex search and fine-tuning processes and are prone to fall into local optimal solutions. To solve this problem, the authors propose a novel channel pruning framework AdaPruner, which can generate corresponding sub-networks adaptively for various budget complexities and efficiently select the initialization weights suitable for the current structure by sparse training once. Experimental results show that the proposed method achieves better performance than previous pruning methods on both commonly used residual networks and lightweight networks on multiple datasets for image classification task. 
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Reinforcement Learning of Spiking Neural Network Based on Knowledge Distillation
ZHANG Ling, CAO Jian, ZHANG Yuan, FENG Shuo, WANG Yuan
Acta Scientiarum Naturalium Universitatis Pekinensis    2023, 59 (5): 757-763.   DOI: 10.13209/j.0479-8023.2023.065
Abstract263)   HTML    PDF(pc) (1417KB)(186)       Save
We propose the reinforcement learning method of Spike Distillation Network (SDN), which uses STBP gradient descent method to realize the knowledge distillation from Deep Neural Network (DNN) to Spiking Neural Network (SNN) reinforcement learning tasks. Experiment results show that SDN converges faster than traditional SNN reinforcement learning and DNN reinforcement learning methods, and can obtain a SNN reinforcement learning model with smaller parameters than DNN. SDN is deployed to the neuromorphology chip, and the power consumption is lower than DNN, proving that SDN is a new and high-performance SNN reinforcement learning method and can accelerate the convergence of SNN reinforcement learning.
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Design and Implementation of Object Detection Acceleration Module Based on an ARM+FPGA Heterogeneous Platform
LI Fang, CAO Jian, LI Pu, XIE Hao, ZHAO Xiongbo, WANG Yuan, ZHANG Xing
Acta Scientiarum Naturalium Universitatis Pekinensis    2022, 58 (6): 1035-1041.   DOI: 10.13209/j.0479-8023.2022.089
Abstract539)   HTML    PDF(pc) (814KB)(234)       Save
Object detection algorithms based on deep learning use big models are difficult to be deployed at the edge. Taking YOLO (you only look once) object detection algorithm as an example, an acceleration module based on an ARM+FPGA heterogeneous platform is proposed. The FPGA chip accelerates the forward process of the compressed model while ARM is responsible for process scheduling. Experiment results show that the peak performance of the system reaches 425.8 GOP/s under 200 MHz working frequency. The system on a Xilinx ZCU102 board achieves a frame rate at 30.3 fps, while the power consumption is 3.56 W. It is also configurable.
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A Hardware Accelerator for SSD Object Detection Algorithm Based on FPGA
XIE Hao, CAO Jian, LI Pu, ZHAO Xiongbo, ZHANG Xing
Acta Scientiarum Naturalium Universitatis Pekinensis    2022, 58 (6): 1015-1022.   DOI: 10.13209/j.0479-8023.2022.096
Abstract738)   HTML    PDF(pc) (1316KB)(277)       Save
A hardware accelerator of object detection algorithm based on FPGA is designed to accelerate the computation of SSD object detection algorithm. Loop tiling and loop unrolling are used to optimize the loops of convolution and pooling, and can be re-configurated in any parallelism. In order to reduce data transmission time, feature maps are reorganized based on AXI, without any hardware resource overhead. After implementing the hardware accelerator to Xilinx ZCU development board, it can accelerate SSD at a performance of 534.72 GOPS, and the inference time is 113.81 ms.
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Post Training Quantization Preprocessing Method of Convolutional Neural Network via Outlier Removal
XU Pengtao, CAO Jian, CHEN Weiqian, LIU Shengrong, WANG Yuan, ZHANG Xing
Acta Scientiarum Naturalium Universitatis Pekinensis    2022, 58 (5): 808-812.   DOI: 10.13209/j.0479-8023.2022.082
Abstract402)   HTML    PDF(pc) (452KB)(249)       Save
In order to improve the performance of post training quantization model, a quantization preprocessing method based on outlier removal is proposed. This method is simple and easy to use. The outliers of weight and activation value are removed only through simple operations such as sorting and comparison, so that the quantization model loses only a small amount of information and improves the accuracy. The experimental results show that the performance can be significantly improved by preprocessing with this method before using different quantization methods.
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Layer Pruning via Fusible Residual Convolutional Block for Deep Neural Networks
XU Pengtao, CAO Jian, SUN Wenyu, LI Pu, WANG Yuan, ZHANG Xing
Acta Scientiarum Naturalium Universitatis Pekinensis    2022, 58 (5): 801-807.   DOI: 10.13209/j.0479-8023.2022.081
Abstract501)   HTML    PDF(pc) (846KB)(203)       Save
Aiming at the problems of long inference time and poor effect of the compression model obtained by the current mainstream pruning methods, an easy-to-use and excellent layer pruning method is proposed. The original convolution layers in the model are transformed into fusible residual convolutional blocks, and then layer pruning is realized by sparse training, therefore a layer pruning method with engineering ease is obtained, which has the advantages of short inference time and good pruning effect. The experimental results show that the proposed layer pruning method can achieve a very high compression rate with less accuracy loss in image classification tasks and object detection tasks, and the compression performance is better than the advanced convolutional kernel pruning methods.
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Pruning and Fine-tuning Optimization Method of Convolutional Neural Network Based on Global Information
SUN Wenyu, CAO Jian, LI Pu, LIU Rui
Acta Scientiarum Naturalium Universitatis Pekinensis    2021, 57 (4): 790-794.   DOI: 10.13209/j.0479-8023.2021.053
Abstract950)   HTML    PDF(pc) (550KB)(164)       Save
In order to solve the problem that convolutional neural network is large and the accuracy loss of the model pruning method is relatively serious, a fine-tuning optimization method for model pruning is proposed. The global information of the original convolutional neural network model is introduced to the post-prune model to make it store the original model information which improves the accuracy of the model after pruning. Experimental results show that for the image classification tasks and target detection tasks, proposed fine-tuning optimization method can obtain greater compression ratio and smaller model accuracy loss. 
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A BFGS-Corrected Gauss-Newton Solver for Bundle Adjustment
ZHAO Shuaihua, LI Yanyan, CAO Jian, CAO Xixin
Acta Scientiarum Naturalium Universitatis Pekinensis    2020, 56 (6): 1013-1019.   DOI: 10.13209/j.0479-8023.2020.098
Abstract1479)   HTML    PDF(pc) (609KB)(235)       Save
Aiming at the problem that the Gauss-Newton (GN) method is sensitive to the initial information matrix in the Bundle Adjustment (BA) model, which leads to limited application scenarios, the paper proposes a novel method BFGS-GN using BFGS (Broyden-Fletcher-Goldfarb-Shanno) algorithm to improve the traditional Gauss-Newton method. When the information matrix of the Gauss-Newton method loses positive definiteness, BFGS algorithm can be used to modify the normal equations, which fundamentally eliminates the mathematical defect that the Gauss-Newton method is sensitive to initial values. Experimental results demonstrate that proposed method is robust to different types of initials. The same accuracy and the number of iterations as GN can be obtained when the initial values are good. As for bad inputs, GN-based BA method cannot work but BFGS-GN can converge to a minimum.
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Design and Implementation of an Asynchronous Low Power RSA Circuit Structure
ZHANG Qihui, CAO Jian, CAO Xixin, YU Dunshan, ZHANG Xing
Acta Scientiarum Naturalium Universitatis Pekinensis    2018, 54 (6): 1351-1354.   DOI: 10.13209/j.0479-8023.2018.046
Abstract808)   HTML    PDF(pc) (2003KB)(204)       Save

An asynchronous low power RSA circuit structure and its modular multiplication circuit structure for smart cards and RFID tags are proposed. By using GTECH optimization scheme and BrzCallMux implementation strategy, ASIC implementation is carried out based on a TSMC 130 nm standard CMOS technology. Experimental results show that the area of the proposed asynchronous low power RSA is only 4% of that of another asynchronous RSA, its average time to perform a cryptographic operation is only 0.216% of that of another asynchronous RSA, and its power consumption is only 16.99% of that of its corresponding synchronous counterpart.

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Improvements on Transient Power Law Model under HBM Stress
CAO Xin, CAO Jian, WANG Yize, WANG Yuan, ZHANG Xing
Acta Scientiarum Naturalium Universitatis Pekinensis    2018, 54 (5): 946-950.   DOI: 10.13209/j.0479-8023.2018.044
Abstract695)   HTML    PDF(pc) (510KB)(85)       Save

An improved model is proposed based on the transient power law model under Human Body Model (HBM) stress. This model can predict the gate oxide breakdown statistically under HBM stress. Through HSPICE simulation tool, the corresponding DC effective voltage on the MOS can be calculated. The scatter chart of the precharge voltage of the HBM circuit with the effective DC voltages of the MOS shows a linear relationship. Using the Laplace transform, the linear relationship is proved. Compared with the existing transient power law model, the improved model reduces the computational complexity under the HBM stress and is easier to predict the MOS gate oxide breakdown statistically. The proposed model provides an important reference for the evaluation of the reliability of the MOS gate oxide under the impact of HBM.

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Diagenesis Types and Evolution of the Lower-Middle Ordovician Carbonates in Yubei Area, Tarim Basin
LIU Hongguang, LIU Bo, ZHANG Xuefeng, CAO Jianhua, HUANG Chenjun, LIU Geyun, WU Shuanglin
Acta Scientiarum Naturalium Universitatis Pekinensis    2018, 54 (2): 373-384.   DOI: 10.13209/j.0479-8023.2017.135
Abstract1174)   HTML1)    PDF(pc) (62505KB)(283)       Save

The Lower-Middle Ordovician carbonate rocks are studied by core observation, thin section observation, geochemical analysis to restore the diagenetic evolution history of the Yubei area, Tarim Basin. Dissolution, dolomitization, silicification and cataclasis are studied and the diagenetic evolution history is divided into four stages. The grained texture dominated limestone in the relative geomorphic high location exposes to the ground and undergoes penecontemporaneous dissolution due to the fluctuation of the sea level. Caves and pores with structural selectivity parallel to the sedimentary bed are generated by the penecontemporaneous dissolution. The dolomitization developed mainly in early diagenetic stage enhances the resistance of carbonates to compaction and pressure solution, which benefits the preservation of early pores and caves. The fractures formed during the Middle-Late Caledonian and Early Hercynian in this stage are mostly closed and filled due to complicated compaction and cementation. Hydrothermal activity in middle diagenetic stage damages the reservoir slightly by the presence of pyrite and dolomite with wavy extinction and saddle structure in the reservoir space. The late diagenetic stage is characterized by the silica and calcareous fluid activity, which fill the early space partially. The development degree of fractures formed during Late Hercynian and Himalayan epoch is weaker than early diagenetic stage. However, the fractures formed during late diagenetic stage keep open due to weak diagenetic transformation and become efficient migration channel and reservoir spaces in Yubei area.

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An Analysis Method of System-Level ESD Model with a TLP Stress Input
WANG Yize, WANG Yuan, CAO Jian, ZHANG Xing
Acta Scientiarum Naturalium Universitatis Pekinensis    2018, 54 (2): 293-298.   DOI: 10.13209/j.0479-8023.2017.146
Abstract1044)   HTML2)    PDF(pc) (1671KB)(329)       Save

Based on the existing equivalent formula of the transmission line pulse (TLP) and IEC 61000-4-2 stresses, the authors propose an analysis method of the system-level model with TLP stress as an input. Compared with the traditional analysis method under system-level IEC stress, the proposed method solves the issue that the calculation of the residual energy flowing into the device under test (DUT) is not accurate enough. Meanwhile, the prediction ability for the failure of the DUT is promoted. This work predicts the failure of the DUT under the mentioned two stresses through SPICE simulation. Furthermore, this work shows the validation through the measured results of the relevant printed circuit boards (PCBs), which confirms the promotion of the aforesaid prediction ability.

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Volumetric Display System Based on FPGA and DLP Technologies
CAO Jian,JIAO Hai,WANG Yuan,ZHANG Xing
Acta Scientiarum Naturalium Universitatis Pekinensis   
Abstract756)      PDF(pc) (2712KB)(473)       Save
A volumetric display system based on FPGA and DLP technologies is raised. FPGA is used to construct the graphical processing unit, controlling and propagating video streams synthesized after image dithering and layer combined algorithms. This video stream is passed down inside the FPGA through SD card controlling unit, DDR2 high speed memory control, pixel frame converter and HDMI high resolution signal transmitting modules. Afterwards, the video stream is captured by the receiving end of the DLP projector, inside the projector’s video decoding module, the digital electrical signal is converted to light signal and projected to a spinning display underneath. This method allows the viewer perceiving a multi-angled 3D image hovering in air without the wearing of special glasses.
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Novel Ultra-Low-Leakage ESD Power Clamp Circuit in Nanoscale Process
WANG Yuan,ZHANG Xuelin,CAO Jian,LU Guangyi,JIA Song,ZHANG Ganggang
Acta Scientiarum Naturalium Universitatis Pekinensis   
Abstract791)      PDF(pc) (665KB)(747)       Save
A novel electrostatic discharge (ESD) power clamp circuit with ultra-low leakage current is proposed. An ESD transient detective circuit with feedback loop is used to reduce the voltage between the bulk and gate of MOS capacitor, which results in a ultra-low leakage current performance of novel circuit. Verified by HSPICE simulation in 65 nm CMOS process, the standby leakage current of novel circuit is 24.13 nA, which is more than two-orders lower than that of the traditional design about 5.42 μA.
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Realization of 6, Tap Finite Impulse Response Interpolation Filter for H.264/AVC Encoder
WANG Qingchun,CAO Xixin,LU Weijun,HE XiaoyanCAO Jian
Acta Scientiarum Naturalium Universitatis Pekinensis   
Abstract633)            Save
It is proposed that four hardware architectures of 6, tap finite impulse response interpolation filter for the design of H.264/AVC encoder (SOC). Moreover, based on comparative analysis of Synopsys Design Compiler to implement the hardware at the same constraint, an efficient half pixel interpolation filter (6, tap FIR) architecture had been given finally.
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Electrical Transport Studies of Sodium Titanate Nanowires
SUN Zhonghua,LIANG Xuelei,CAO Jianjun,CHEN Qing,ZHANG Zhiyong,PENG Lianmao
Acta Scientiarum Naturalium Universitatis Pekinensis   
Abstract667)            Save
Individual sodium titanate nanowire-based device is fabricated via e-beam lithography techniques. The authors measure their electrical transport properties in air and in vacuum respectively and find that the electrical transport of sodium titanate nanowires devices is affected. This is attributed to oxygen adsorption on the surface of nanowire. In addition, the authors study ultraviolet (UV) light response of sodium titanate nanowire-based devices and find that UV light may induce a large photoconductivity. The work shows that sodium titanate nanowires may be used potentially as gas sensors and photoelectric sensors.
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